1. Field
Example embodiments relate to a semiconductor memory device and/or a method thereof, and for example, to a memory device employing dual clocking for outputting a systematic code and/or a method thereof.
2. Description of Related Art
In digital data transfer systems, detecting and correcting bit errors caused during transmission without requiring retransmission of data which contains errors is preferable. In conventional error correction systems, a transmitter generates a code in which certain redundant check bits are added to original data that is to be transmitted.
In a channel coding theory, a systematic code including original data and redundant parity bits associated with the original data is defined.
As the operating speeds of semiconductor memory devices increase, a channel bit error rate (BER) increases. Accordingly, a technique for detecting and correcting channel errors is required. Accordingly, semiconductor memory devices use a method of internally generating a systematic code and transmitting the systematic code to external controllers.
In a systematic code, data output from memory cell arrays becomes original data, and bits obtained by coding the output data of the memory cell arrays become redundant parity bits.
Because the redundant parity bits are generated by logic circuits performing an exclusive OR operation on the original data, a significant latency is required. Accordingly, in semiconductor memory devices which output systematic codes, a read data latency is higher.